1. Field of the Invention
The present invention relates to a high frequency amplification circuit and a mobile communication terminal using the same, and more specifically to a high frequency amplification circuit provided in a high frequency circuit block or the like of a transmission section of a mobile communication terminal for performing gain control in accordance with a given control voltage, and the mobile communication terminal using the same.
2. Description of the Background Art
Recently, in the field of mobile communication, composite cellular phone terminals compatible to a plurality of communication systems are becoming main stream mobile communication terminals. Examples of such composite cellular phone terminals are compatible to the PDC (Personal Digital Cellular) system and the W-CDMA (Wide band Code Division Multiple Access) system. The PDC system has an advantage of providing a wide service area, and the W-CDMA system has an advantage of providing a high data communication rate. The composite cellular phone terminals compatible to both of these systems have the advantages of both of the systems, and thus are expected to be rapidly spread in the future. Aside from such terminals, communication systems compatible to multiple bands using the W-CDMA system are now being studied.
Such a mobile communication terminal uses a plurality of signals having different frequencies as carrier waves, and therefore includes a plurality of high frequency circuit blocks corresponding to the respective frequencies (see FIG. 2 described below). Meanwhile, in order to reduce the size of the mobile communication terminals, it is considered important to reduce the number of components on the substrate and thus reduce the size of the high frequency circuit blocks.
FIG. 30 is a block diagram showing a structure of a conventional high frequency amplification circuit which is included in a mobile communication terminal compatible to a plurality of communication systems. In FIG. 30, matching circuits 901, 904 and 906 are impedance matching circuits for performing impedance conversion. A high frequency signal which is input from a signal input terminal 911 is input to a gain control circuit 902 via the matching circuit 901. The gain control circuit 902 attenuates the input signal in accordance with a control voltage VC applied to a gain control terminal 913 and outputs the attenuated signal. The output signal from the gain control circuit 902 is amplified by an amplifier 903. The output signal from the amplifier 903 is input to an amplifier 905 via the matching circuit 904, and is amplified by the amplifier 905. The output signal from the amplifier 905 is output from a signal output terminal 912 via the matching circuit 906. The control voltage VC applied to the gain control terminal 913 is generated by converting a digital control signal, which is output from a control section (not shown), into an analog signal by a D/A converter.
FIG. 31 is a graph illustrating the relationship between the control voltage and the output voltage in the high frequency amplification circuit shown in FIG. 30, the relationship being obtained where the input power is constant. As shown in FIG. 31, the output power is approximately fixed at PL when the control voltage VC is lower than VL, is approximately fixed at PH when the control voltage VC is higher than VH, and continuously changes in accordance with the control voltage VC when the control voltage VC is equal to or higher than VL and equal to or lower than VH.
By using a high frequency amplification circuit having such characteristics, the transmission power of the mobile communication terminal can be controlled. For example, with the time division multiple access system represented by the PDC system, burst communication is performed between a mobile communication terminal and a base station. Therefore, as shown in FIG. 32, the power of a signal transmitted between the mobile communication terminal and the base station is high during a communication period and low during a non-communication period. Such a transmission signal can be easily generated by supplying the gain control terminal 913 of the high frequency amplification circuit (FIG. 30) with a first control voltage during the communication period and with a second control voltage lower than the first control voltage during the non-communication period.
A gain control circuit included in a high frequency circuit block of a transmission section of a mobile communication terminal as described above is configured by using, for example, a MESFET (Metal Semiconductor Field Effect Transistor). In a gain control circuit including an FET, gain control is performed by the FET operating as a variable resistor. A conventionally known gain control circuit including an FET is, for example, described in Japanese Laid-Open Patent Publication No. 10-256853.
FIG. 33 is a circuit diagram showing a conventional gain control circuit 920 described in Japanese Laid-Open Patent Publication No. 10-256853. The gain control circuit 920 shown in FIG. 33 includes resistors 921 and 922 and an FET 923 for attenuation control, and acts as a variable attenuation circuit. As shown in FIG. 33, the resistor 921 is provided between a signal input terminal 931 and a signal output terminal 932. The signal input terminal 931 is also connected to one end of the resistor 922, and the other end of the resistor 922 is connected to a positive power source 924. The FET 923 is provided parallel to the resistor 921. The end of the resistor 921 closer to the signal input terminal 931 is connected to a source terminal of the FET 923, and the end of the resistor 921 closer to the signal output terminal 932 is connected to a drain terminal of the FET 923. A gate terminal of the FET 923 is connected to an attenuation control terminal 933 via a resistor 925. A control voltage VC is applied to the attenuation control terminal 933 for adjusting an attenuation in the gain control circuit 920.
Hereinafter, the voltage value of the power source 924 will be represented as Vref, the threshold voltage of the FET 923 will be represented as Vth, the voltage applied to the attenuation control terminal 933 will be represented as VC, and the potentials at the gate terminal, the source terminal and the drain terminal of the FET 923 will be respectively represented as Vg, Vs and Vd. The maximum value of the control voltage VC at which the FET 923 is in a disconnected state (i.e., a state where the resistance value between the source terminal and the drain terminal is in a high impedance state) will be represented as VC(off). The minimum value of the control voltage VC at which the FET 923 is in a conductive state (i.e., a state where the resistance value between the source terminal and the drain terminal is in a low impedance state) will be represented as VC(on). The difference between VC(off) and VC(on) will be represented as Vw.
When the FET 923 is just put into the disconnected state (i.e., when the FET 923 will not be in the disconnected state if the potential at the gate terminal becomes higher than the current value), the potentials at the gate terminal and the source terminal have a relationship represented by expression (1).Vg−Vs=Vth  (1)
With the voltage drop by the resistors 921, 922 and 925 being ignored, the potentials at the terminals of the FET 923 are represented by expressions (2) through (4) using the voltage value Vref of the power source 924 and VC(off).Vg=VC(off)  (2)Vs=Vref  (3)Vd=Vref  (4)
By substituting expressions (2) and (3) for expression (1), expression (5) is obtained using voltage VC(off). VC(on) is represented by expression (6).VC(off)=Vref+Vth  (5)VC(on)=Vref+Vth+Vw  (6)
According to expressions (2) through (5), it is appreciated that the potentials at the terminals of the FET 932 when the FET 932 is just put into the disconnected state are determined by the threshold voltage Vth of the FET 923 and the voltage value Vref of the power source 924.
In the conventional gain control circuit shown in FIG. 33, the control voltage VC is changed in the state where the voltage value Vref of the power source 924 is fixed, so that the potential between the gate terminal and the source terminal of the FET 923 is changed, and the ON resistance value between the source terminal and the drain terminal of the FET 923 is changed. In this behavior, the attenuation between the signal input terminal 931 and the signal output terminal 932 is changed in accordance with the control voltage VC. Thus, the gain control can be performed based on the control voltage VC.
However, the above-described conventional gain control circuit has the following problems. As described above, expression (5) is fulfilled with the conventional gain control circuit. However, when the threshold voltage Vth of the FET 923 is varied due to, for example, inconsistencies in the production process or the operating temperature change, the control voltage VC(off) at which the FET 923 is just put into the disconnected state is varied. For this reason, with the conventional gain control circuit, when the threshold voltage of the FET 923 is varied due to, for example, inconsistencies in the production process or the operating temperature change, the attenuation of the high frequency signal in the FET 923 is varied and thus the gain of the high frequency amplification circuit is varied.
In addition, with the conventional gain control circuit, the dynamic range is determined by the difference between (i) the ON resistance between the source terminal and the drain terminal of the FET 923 when the FET 923 is in the disconnected state and (ii) the ON resistance when the FET 923 is in the conductive state. In order to broaden the dynamic range, the resolution of the control voltage needs to be improved, which necessitates connection of a D/A converter having a high resolution of output voltage to the gain control terminal. This enlarges the circuit scale of the D/A converter and thus increases the control parameters of the attenuation, which complicate the control circuit.